1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a manufacturing method thereof, and more particularly to the improvement of structures of a non-volatile semiconductor memory device.
2. Description of the Background Art
Conventionally, in a stacked gate type non-volatile semiconductor memory device having a floating gate electrode and a control gate electrode, in order to improve the performance thereof, capacity between the floating gate electrode and the control gate electrode needed to be sufficiently larger than that between the floating gate electrode and a substrate. The performance of a semiconductor device as used herein means that the voltage in data writing and erasure is lowered, or writing and erasing time is shortened.
The capacity between the floating gate electrode and the control gate electrode is roughly determined by overlapping area of the floating gate electrode with the control gate electrode and thickness of an insulating film (usually a stacked film composed of what is called ONO film of oxide film/nitride film/oxide film) between the floating gate electrode and the control gate electrode. Insulating film should be made thin to increase the capacity between the floating gate electrode and the control gate electrode. In order to retain the charges stored in the floating gate electrode, however, the film cannot be made too thin. In addition, as cell size is reduced, with conventional structures, it is becoming difficult to secure sufficient overlapping area of the floating gate electrode with the control gate electrode.
FIG. 17 shows a cross-sectional structure of a conventional AND type non-volatile semiconductor memory device. In a prescribed position on the main surface of semiconductor substrate 20, element-isolating regions 1 are formed with a prescribed spacing to define an active region. In the active region, T-shaped floating gates 3, 7 made of polysilicon (polycrystalline silicon) film are provided on the main surface of semiconductor substrate 20, with a gate insulating film 2 interposed. Floating gate electrode 3 is provided in such a way that it is embedded in interlayer insulating film 6, and floating gate electrode 7 contacts floating gate electrode 3 and is provided in a prescribed pattern on interlayer insulating film 6. Provided on floating gate electrode 7 is insulating film (ONO film) 9, on which control gate electrode 12 is provided. Interlayer insulating film 14 is provided thereon. Floating gate electrode is in T-shape so that the overlapping area of the floating gate electrode with the control gate electrode is sufficiently secured.
Meanwhile, reduction of cell size consequently causes securable overlapping length (dimension a in FIG. 17) in transverse direction to be shortened and overlapping area to be reduced. Accordingly, in the case cell size reduces, in order to increase overlapping area to secure capacity between the floating gate electrode and the control gate electrode, a method in which film thickness (shown as b in the figure) of floating gate electrode 7 extending transversely is increased, as shown in a cross-sectional view of FIG. 18, to increase overlapping area on the side surface has been adopted (a+2xc3x97b in the figure is overlapping length, word line width (in a direction of depth) is overlapping width, and thus overlapping area=overlapping lengthxc3x97overlapping width).
When film thickness (shown as b in the figure) of floating gate electrode 7 extending transversely is increased, polysilicon film thickness (shown as c in the figure) from the upper surface of gate oxide film 2 to the lower surface of insulating film 9 is consequently increased. In etching in a direction of word line (left-to-right direction in the figure), the portion with the maximum film thickness of this polysilicon film must be infallibly etched. However, when etching period is long, a problem will arise that word line may also be etched transversely (in a direction perpendicular to the sheet surface) to cause word line width to be smaller.
In addition, since film thickness of gate oxide film 2 provided below floating gate electrode 3 made of polysilicon is small, there is a limitation for overetching time and time control thereof is difficult. Therefore, gate oxide film 2 tends to be etched as far as Si substrate, or generation of polysilicon residue is likely.
An object of the present invention is to provide a non-volatile semiconductor memory device and a manufacturing method thereof which allows overlapping area of a floating gate electrode with a control gate electrode to be sufficiently secured while not enlarging a portion with the maximum film thickness of the floating gate electrode made of polysilicon.
A non-volatile semiconductor device according to the present invention includes: a semiconductor substrate; a gate insulating film provided on a main surface of the semiconductor substrate; an interlayer insulating film provided on the gate insulating film; a first floating gate electrode provided to be in contact with the gate insulating film and embedded in the interlayer insulating film with an upper surface only being exposed; a second floating gate electrode provided on the interlayer insulating film; a third floating gate electrode provided to cover the first floating gate electrode, the second floating gate electrode and the interlayer insulating film so as to electrically connect the first floating gate electrode and the second floating gate electrode; an insulating film provided to cover the third floating gate electrode; and a control gate electrode provided to cover the insulating film; wherein the second floating gate electrode has a bottom surface positioned to be higher than an upper surface of the first floating gate electrode.
In addition, a method of manufacturing a non-volatile semiconductor device according to the present invention includes the steps of: forming a gate insulating film on a main surface of a semiconductor substrate; forming on the gate insulating film a first floating gate electrode having a periphery surrounded by an interlayer insulating film; forming a semiconductor layer on upper surfaces of the interlayer insulating film and the first floating gate electrode; etching the floating gate electrode and the semiconductor layer so as to position the upper surface of the first floating gate electrode to be lower than the upper surface of the interlayer insulating film and to have the semiconductor layer left solely on the upper surface of the interlayer insulating film, and forming a second floating gate electrode with remaining semiconductor layer; forming a third floating gate electrode to cover the first floating gate electrode, the interlayer insulating film and the second floating gate electrode; forming an insulating film to cover the third floating gate electrode; and forming a control gate electrode to cover the insulating film.
According to the non-volatile semiconductor device and the manufacturing method thereof, by disposing the bottom surface of the second floating gate electrode to be higher than the upper surface of the first floating gate electrode, three-layered structure of the first floating gate electrode located below, the second floating gate electrode located above and the third floating gate electrode coupling the first floating gate electrode and the second floating gate electrode is implemented. In addition, by disposing the first floating gate electrode and the second floating gate electrode at positions different in a direction of height, an inclined portion can be produced in the third floating gate electrode. As a result, contact length of the floating gate electrode with the control gate electrode is extended, and overlapping area of the floating gate electrode with the control gate electrode can be increased.
Further in the present invention of the non-volatile semiconductor device, preferably, the interlayer insulating film is provided with a flat surface which is substantially as high as the upper surface of the first floating gate electrode.
Moreover in the present invention of the non-volatile semiconductor device, preferably, the interlayer insulating film is provided with an inclined surface extending from the upper end portion of the first floating gate electrode to the upper surface of the first interlayer insulating film. According to this configuration, the second floating gate electrode is sufficiently distanced from a diffused layer interconnection region provided on the semiconductor substrate. Therefore, lowering of the coupling ratio of the non-volatile semiconductor device due to the increase of parasitic capacitance between the second floating gate electrode and the diffused layer interconnection region can be prevented.
Further in the present invention of the non-volatile semiconductor device, preferably, the first floating gate electrode and the second floating gate electrode are positioned spaced apart, and the third floating gate electrode is provided to establish electrical connection between the first floating gate electrode and the second floating gate electrode.
With this configuration, film thickness as a floating gate electrode will not be as large as in a conventional structures. As a result, overlapping area of the floating gate electrode with the control gate electrode can be sufficiently secured without a portion with the maximum film thickness of the floating gate electrode being enlarged.
In addition in the present invention of the non-volatile semiconductor device and the manufacturing method thereof, preferably, the second floating gate electrode has a film thickness smaller than that of the first floating gate electrode. Thus, in etching the floating gate electrode in a word line direction, it will be possible to avoid excessive overetching of the thin gate oxide film.
In the present invention of the non-volatile semiconductor device, preferably, the third floating gate electrode is composed of silicon containing an n-type impurity.
Moreover in the present invention of the non-volatile semiconductor device and the manufacturing method thereof, preferably, the third floating gate electrode contains a larger amount of the n-type impurity than the first floating gate electrode. Thus, by diffusing impurity from the third floating gate electrode toward the first floating gate electrode, concentration of the first floating gate electrode with low impurity concentration is increased, and depletion due to the applied voltage in cell operation can be prevented.
In addition in the present invention of the non-volatile semiconductor device and the manufacturing method thereof, preferably, the second floating gate electrode contains a larger amount of the n-type impurity than the first floating gate electrode. Thus, by diffusing impurity from the second floating gate electrode, low impurity concentration of the first floating gate electrode is increased and depletion when a voltage is applied in cell operation can be prevented.
Further in the present invention of the method of manufacturing a non-volatile semiconductor device, preferably, in the step of forming the second floating gate electrode, an etchant having selective etching rate 1:1 in etching the first floating gate electrode and the interlayer insulating film is used for etching the first floating gate electrode and the semiconductor layer. Thus, a flat surface which is substantially as high as the upper surface of the first floating gate electrode can be formed on the interlayer insulating film.
In addition in the present invention of the method of manufacturing a non-volatile semiconductor device, preferably, in the step of forming the second floating gate electrode, an etchant having selective etching rate 5:1 or higher in etching the first floating gate electrode and the interlayer insulating film is used for etching the first floating gate electrode and the semiconductor layer. Thus, an inclined surface which extends from the upper end portion of the first floating gate electrode to the upper surface of the first interlayer insulating film can be formed.
Moreover in the present invention of the method of manufacturing a non-volatile semiconductor device, preferably, the first floating gate electrode, the second floating gate electrode and the third floating gate electrode are of amorphous silicon.
Further in the present invention of the method of manufacturing a non-volatile semiconductor device, preferably, the first floating gate electrode, the second floating gate electrode and the third floating gate electrode are of polysilicon.
In the present invention of the method of manufacturing a non-volatile semiconductor device, preferably, the interlayer insulating film is CVD oxide film.
In the method of manufacturing a non-volatile semiconductor device of the present invention preferably further includes the step of forming a word line, and after removing the third, second and first floating gate electrode material deposited in an opening formed in the word line, removing the first floating gate electrode material remaining on the bottom surface portion of the opening. Preferably, dilute ammonia solution is used for removing the first floating gate electrode material remaining on the bottom surface portion of the opening. Thus, removal of the floating gate electrode material remaining on the bottom surface portion in the opening can be ensured.